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W631GG6KB
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
Tn
CK#
CK
Command *3
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
READ
t WTR *5
Address *4
DQS, DQS#
Bank
Col n
t WPRE
t WPST
Bank
Col b
DQ *2
Din
n
Din
n+1
Din
n+2
Din
n+3
WL = 5
RL = 6
Notes:
TIME BREAK
TRANSITIONING DATA
DON'T CARE
1.
2.
3.
4.
5.
BC4, WL = 5, RL = 6.
Din n = data-in from column n; Dout b = data-out from column b.
NOP commands are shown for ease of illustration; other commands may be valid at these times.
BC4 setting activated by MR0 A[1:0] = 10 during WRITE command at T0 and READ command at Tn.
t WTR controls the write to read delay to the same device and starts with the first rising clock edge after the last write data
shown at T7.
Figure 45 – WRITE (BC4) to READ (BC4) Operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
Tn
CK#
CK
Command *3
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PRE
t WR *5
Address *4
Bank
Col n
DQS, DQS#
t WPRE
t WPST
DQ *2
Din
n
Din
n+1
Din
n+2
Din
n+3
WL = 5
Notes:
TIME BREAK
TRANSITIONING DATA
DON'T CARE
1.
2.
3.
4.
5.
BC4, WL = 5, RL = 6.
Din n = data-in from column n; Dout b = data-out from column b.
NOP commands are shown for ease of illustration; other commands may be valid at these times.
BC4 setting activated by MR0 A[1:0] = 10 during WRITE command at T0.
The write recovery time (t WR ) referenced from the first rising clock edge after the last write data shown at T7. t WR specifies
the last burst write cycle until the precharge command can be issued to the same bank.
Figure 46 – WRITE (BC4) to PRECHARGE Operation
Publication Release Date: Dec. 09, 2013
Revision A05
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